A‑01 · Bank VCCO
Preserve the intended receiver voltage. Move the output to a suitable bank or use an approved level interface from the 1.2 V bank.
Close with the revised rail sheet, receiver limits and a pin report covering the bank. AMD UG571
Sample redacted pre-PCB sign-off report
Aster RF Capture Card
Rev A · clean-room demonstration. The board, ball numbers, quad names and circuit identifiers are synthetic. This sample illustrates the evidence and closure criteria provided with a five-business-day OFFER-A audit. Example fixed scope: USD 4,500.
HOLD BEFORE FABRICATIONFive Critical Respin-Stoppers · one High finding
Scope covers a Kintex UltraScale+ class FPGA, an ADRV9026-class RF peer, DDR4 and a 10GbE SFP+ uplink. Inputs include 12 FPGA ports, 13 BOM records, four GT directions, two reference clocks, five RF controls and 25 literal XDC assignments.
Findings at a glance
| ID / severity | Evidence | Owner and disposition |
|---|---|---|
| A‑01 · Critical | Sheet 06. RF_STATUS_DRV is LVCMOS18 on U1 AA12. HP bank 65 is supplied at 1.2 V. | Hardware. Reassign the pin or reconcile the interface and bank rail. |
| A‑02 · Critical | Sheet 03. RF_SYSREF_P maps to AF14 (N) and RF_SYSREF_N to AE14 (P). | Hardware and FPGA. Restore polarity and verify the capture edge. |
| A‑03 · Critical | Sheet 02. JESD_DAC_L0 maps U1 GTY TX to U2 JTX0, a transmit pair. | Hardware. Map U1 TX to a verified receiver at U2. |
| A‑04 · Critical | Sheet 02. JESD_ADC_L0 fits R203/R204 while C203/C204 are DNP. | Hardware and assembly. Restore series AC coupling on both conductors. |
| A‑05 · Critical | Sheet 02. XO_156M25 enters Q0 and reaches Q0/Q1 in the supplied route map. JESD uses Q2. | FPGA and hardware. Reconcile clock source, quad placement and PLL. |
| A‑06 · High | Draft XDC. DDR4_CKE uses AB19 / LVCMOS18. The schematic and package plan specify AC19 / SSTL12. | FPGA. Review the two literal XDC edits and the memory pin plan. |
Hardware closure evidence
A‑02 · SYSREF polarity
Correct both package legs and check the sampling relationship between the device clock and SYSREF for the selected JESD subclass.
Close with P/N continuity, the corrected package mapping and the agreed capture-edge check. ADI UG-1727
A‑03 · TX-to-TX lane
Map the FPGA transmitter to the intended RF receiver. Confirm the reverse direction separately using electrical endpoint roles.
Close with the revised lane matrix, observed nets and end-to-end P/N trace. AMD UG578
A‑04 · AC coupling bypass
R203/R204 create a DC path while the capacitors are absent from the fitted variant. Review the endpoint biasing and select the intended series population.
Close with the fitted BOM, both series paths and the approved capacitor value, package and placement. ADI UG-1727
A‑05 · MGTREFCLK reach
The plan lists a 245.76 MHz candidate on Q2. Qualify its rate, PLL operating point and jitter budget before selecting it, or document an alternate reachable placement.
Close with the exact part, dedicated input, quad assignment and a Vivado GT configuration report. AMD UG578
A‑06 · DDR4 constraint repair
The pin plan confirms AC19 in a 1.2 V bank and an SSTL12 output. The adjacent sampled POD12 data lane has its reference covered by INTERNAL_VREF 0.84. The proposed change targets only DDR4_CKE.
-set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports {DDR4_CKE}]
+set_property -dict { PACKAGE_PIN AC19 IOSTANDARD SSTL12 } [get_ports {DDR4_CKE}]Close with an updated Vivado pin report and a successful memory-IP I/O plan check. The patch leaves A‑01 through A‑05 open.
Release handoff
- Hardware issues one corrected schematic and fitted BOM with bank, lane and coupling evidence.
- FPGA reconciles the new pin plan, applies the reviewed XDC diff and validates GT placement and memory I/O.
- Layout reviews return paths, skew, stackup and coupling footprints against the interface limits.
- The release owner records closure evidence for each finding and approves the identified revision.
This is a schematic and constraint audit. Timing closure, SI/PI simulation, full DDR4 byte-lane placement and lab bring-up are separate checks on the complete design.
References
AMD UG571 · SelectIO · AMD UG578 · GTY · AMD UG903 · XDC · ADI UG-1727 · JESD204 · SNIA · SFP+ specifications