BELOUSOVHARDWARE SIGN-OFF

Independent principal practice

FPGA sign-off
before fabrication.

A five-day asynchronous review of high-speed FPGA and RF schematics, pinout and Vivado constraints. One principal architect, one board revision, one actionable release decision.

Read the sample report Scope a review
$3,500–$7,500Fixed scope · five business days from agreed inputs
ASTER RF CAPTURE CARDREV A · SYNTHETIC
5 critical findings1 high finding2 XDC changes

OFFER-A · Pre-PCB review

Check the interfaces that can force a respin.

Bring a draft schematic, pin export, BOM and XDC. Leave with a ranked issue list tied to the affected sheet, component or net, and a reviewable constraint diff.

SELECTIO

Bank and pin plan

VCCO, VREF, I/O standards, differential P/N, dedicated clock inputs and reset. Check the exact FPGA part, package and speed grade.

SERIAL LINKS

GT and reference clocks

JESD204B/C, 10G/25GbE and PCIe. Review lane direction and quad placement, oscillator reach, AC coupling and polarity.

RELEASE HANDOFF

Evidence and fixes

Critical respin-stoppers, suggested XDC edits and closure criteria for hardware, FPGA and layout owners.

Planning scenario for a complex respin · $50k–$150k and up to three months. Use the budget and schedule assumptions for your own program.

Engineering examples

Proof you can inspect.

Clean-room examples use synthetic inputs or public specifications. Each example defines the evidence required to pass.

SYNTHETIC REPORT

Aster RF capture card

Kintex UltraScale+, ADRV9026-class JESD204C, DDR4 and 10GbE SFP+. The audit found five critical hardware defects and one high XDC defect.

Inspect the six findings

VERIFICATION PLAN

Ethernet-to-host data path

10G/25G UDP into PCIe Gen3 DMA. A sequence-numbered load test exercises backpressure, descriptor wrap and reset recovery. Example acceptance target is zero packet loss over the agreed rate, duration and frame mix.

Zynq MPSoC / RFSoC · Arria 10

VERIFICATION PLAN

Timing-critical control and entropy

Source-synchronous AD9361 capture on Zynq‑7000. A separate commercial security scope can trace ML‑KEM/ML‑DSA known-answer tests and entropy health checks to public NIST requirements.

FIPS 203 · FIPS 204 · SP 800-90B

Principal-led delivery

One revision. Four steps.

Vadim Belousov reviews the schematic and owns the technical handoff. The offer_a_engine runs deterministic schematic and XDC checks. Verilator regression and STA checks can be scoped when the relevant design files and tools are available.

  1. Agree the scope

    Identify the FPGA part, board revision, link rates, release date and permitted civilian end use.

  2. Review the inputs

    Exchange the agreed schematic, BOM, XDC and lane or clock plan through an approved channel.

  3. Deliver on day five

    Receive the findings, evidence, owners, patch and release checklist.

  4. Close the issues

    Use the acceptance criteria to verify fixes against the revised board and implementation reports.

Follow-on engineering · planned

Hardware-in-the-loop bring-up.

The planned Yerevan HIL Pod would host approved customer boards in a Tier III facility after colocation, shipping and access are agreed. Scope can include isolated access, instrumented link bring-up and reproducible regression logs.

Scope your audit

Start with the board brief.

One revision, intended end use and release date are enough for an initial scope. Share design files through the agreed secure channel after scope and access are set.

Direct inquiry email is being set up.